Implementation of Flip Chip and Chip Scale Technology

This leading-edge document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Co-developed by IPC, EIA, MCNC and Sematech. 105 pages. Released January 1996.

Implementation of Flip Chip and Chip Scale Technology

Internationally adopted, this version of J-STD-012 is produced by IPC and IEC. This leading-edge document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Co-developed by IPC, EIA, MCNC and Sematech. 105 pages. Released January 1996.

Semiconductor Design Standard for Flip Chip Applications

This new standard addresses semeconductor flip chip design requirements. Provides information intended for applications utilizing standard semiconductor substrates, materials, assembly and test methods commensurate with established fabrication, bumping, test and handling practices. Covered in the standard are electrical, thermal and mechanical chip design parameters and methodologies, as well as the reliability aspects associated with these conditions and processes. The information applies to all new designs as well as modifications of non-flip chip designs. 45 pages. Released April 1999.

Performance Standard for Flip Chip/Chip Scale Bumps

This new standard establishes construction detail requirements for bumps and other terminal structures used for Flip Chip and Chip Scale carriers. The specific standards for different terminations are appropriately matched to a particular interconnection process and include such diverse terminations as solder bumps, columns, non-melting stand-offs and conductive polymer deposits. The document articulates a set of designations and expectations for product performance for the manufacture and the user of flip chip or chip scale devices. Recommendations are provided for options and flexibility to implement best commercial practices and evolving process improvements. 31 pages. Released April 1999.

Implementation of Ball Grid Array and Other High Density Technology

This document establishes the requirements and interactions necessary for printed board assembly processes for interconnecting high performance/high pin count IC packages Includes information on design prinples, material selection, board fabrication, assebly technology, testing strategy and reliability expectations based on end-use environments. Co-produced with EIA, MCNC and Sematech. 123 pages. Released Augest 1996.

IPC Members: $35

Implementation of Ball Grid Array and Other High Density Technology

Internationally adopted, this version of the IPC-J-STD-013 is produced by IPC and IEC. This document establishes the requirements and interactions necessary for printed board assembly processes for interconnecting high performance/high pin count IC packages Includes information on design prinples, material selection, board fabrication, assebly technology, testing strategy and reliability expectations based on end-use environments. Co-produced with EIA, MCNC and Sematech. 123 pages. Released Augest 1996.

IPC Members: $100

Guidelines for Chip-on-Board Technology Implementation

Discusses chip types, board selection, design issues and thermal transfer methods for COB applications. Details wire bonding, TAB and flip chip designs and provides information on mounting materials, including adhesives, wires and various mechanical bonding techniques. 37 pages. Released November 1990.

IPC Members: $25

An Introduction to Tape Automated Bonding Fine Pitch Technology

This document, co-developed by the IPC, EIA and ASTM, represents a comprehensive report on fine pitch technology with an emphasis on tape automated bonding and design rules. Subjects include land pattern design, types of encapsulation, TAB tape format, assembly techniques and the advantages and disadvantages of FPT. 54 pages. Released by the Surface Mount Council, January 1989.

IPC Members: $30

Chip Mounting Technology (CMT)

Status of the technology discussion on the various methodologies for mounting and interconnecting active devices to a variety of substrate materials are summerized in this document. Reviews the current mounting techniques of tape automated bonding (TAB), chip on board (COB) and flip chip. Examinations of the most commonly used substrate options of laminate, ceramic and silicon are also reviewed. Editor: John Biancini, Intercon Corporation.. 33 pages. Released by the Surface Mount Council, August 1993.

IPC Members: $30

Guidelines for Multichip Module Technology Utilization

Provides information on multichip module technology, including parametric data, design and manufacturing information and a proposed categorization of the various approaches to multichip interconnect substrate technologies based on dielectric "family." 120 pages. Released August 1992.

IPC Members: $35